Two new workspaces move a design from an idea to working RTL: start from a vetted module, or draw the logic as a block diagram. Both feed the same Synthesis, Pin Mapping, and Bitstream flow as hand-written files.
IP Library
What it does
Adds bundled, parameterized modules (counter, PWM, synchronizer, debouncer, FIFO, UART, SPI master, I²C byte writer, VGA timing) in Verilog or SystemVerilog. Set parameters, preview the generated source, and add it with its license and an optional testbench.
The gap
Peripheral RTL is usually copied from old projects or forums, with no record of its version, its parameters, or what you changed afterward.
Who it is for and how it fits in
Who it is for
Students and makers wiring up a first UART or PWM, and engineers who want a checked starting point.
In the app
Its own dock destination for saved projects. It shows verified board pins, connects a module to your top level through a reviewed wrapper, rejects changes to modified files, and is available to AI Design Studio in Edit mode.
A canvas for ports, logic, multiplexers, registers, project modules, and IP entries. Wire them together, group them into reusable modules, and let Allora check widths, loops, and clock-domain crossings before it generates deterministic RTL. Probe signals in a stimulus testbench and export the diagram as SVG or PNG.
The gap
The step between sketching a design on paper and writing RTL. Blocks keeps the diagram and the code linked, so selecting a node finds its generated lines and the reverse.
Who it is for and how it fits in
Who it is for
Learners building intuition for digital logic, and engineers sketching glue logic or data paths before committing to code.
In the app
A dock destination right after Register Builder. Diagrams save in the project, and the generated RTL flows to Synthesis, Pin Mapping, and Bitstream. AI Design Studio proposes edits as drafts you accept or reject.
Write RTL, simulate a RISC-V system, inspect synthesized logic, and build for supported FPGAs. The tools share one desktop workspace and are connected through The Allora Link.
Editor shows RTL source, project files, and the shared workspace dock. Select the image to view the full interface.
Allora Link
A Suite of Design Tools
Allora Link covers AI-assisted design, RISC-V system simulation, virtual hardware, memory and register generation, timing analysis, a bundled IP Library, and Blocks diagrams. Select a tool to see what it does and how its interface looks.
Allora Link uses third-party engines and cores, including Codex, Yosys, Verilator, PicoRV32, and SERV.
Workspace
The FPGA workflow in one desktop app
Allora Link sits alongside the standard FPGA workflow: editing, simulation, synthesis, pin mapping, bitstream generation, and programming.
Write and simulate
Edit Verilog or SystemVerilog. Create a clock and reset testbench scaffold, inspect waveforms, and interact with virtual hardware.
Map and migrate
Assign buses with a preview and undo. Move a design into a separate board project with the Board Migration Assistant, then review any unresolved mappings.
Build and inspect
Synthesize, place and route, and pack bitstreams with the open toolchain. Reuse cached synthesis results, and review timing, artifact details, and resource and frequency trends in Build History.
Projects and conversations
Publish projects to GitHub, return to saved AI conversations, and move between sections with the shared dock. Serial Monitor and Live Register Shell are available in Program.
Board catalog
Supported FPGA boards
The catalog lists boards with open build flows and a larger set of pin mappings. Listing a board describes software support only. Note that physical programming has not been verified.
Explore FPGA boards… open build entries and … pin-mapping entries
Open build flowPin mapping
No boards match that search.
Beta
About the beta
Allora is a free app under active development. Features are still changing, and no board’s programming flow has been fully verified on physical hardware yet. A successful build or simulation does not guarantee a working board program.
Download the installer, then test Allora with a supported board. Report what worked and what did not. Include your board and revision, macOS version, the steps you followed, and relevant logs so the result can be reproduced. Tester feedback helps Allora improve.
