Create and edit RTL
Save real project files, update existing designs, and keep the work inside your project.
FPGA Development Environment
RTL.
Virtual Simulator.
Full FPGA Build
and
Program Pipeline.
Allora brings the open FPGA workflow into one desktop environment. Design and simulate your hardware virtually, then synthesize, place and route, and program all supported open-hardware FPGA boards without leaving the app. Now with an AI Design Studio natively integrated into the app, powered by Codex after you sign in.
Write RTLRun simulationsBuild hardware
One conversation. Real project files. Tools that do the work.
Why Allora
The whole FPGA workflow.
One place to think.
Your editor, waveforms, virtual hardware, synthesis, constraints, and programming share the same project. Move between workspaces from one dock, with native AI a click away.
Native AI Design Studio
Describe the idea.
Build it with Codex.
Codex is built into Allora. Sign in with your account, choose a model and reasoning level, and work with an AI that can act across your FPGA workflow.
Native integration
From a prompt to a real project.
Create a design, refine existing RTL, or troubleshoot a failing testbench. Codex reads and edits your project, calls Allora’s tools, and returns results you can open in the workspace.
-
01
Sign in
Connect your Codex account in Allora.
-
02
Describe what you need
Start from an idea or your current project.
-
03
Inspect the work
Open files, waveforms, and build results.
Test and troubleshoot
Run testbenches and interactive simulation. Bring recent project errors into the conversation when you need help.
Take the design further
Look up boards, assign verified pins, inspect synthesis, and generate bitstreams with Allora’s tools.
See what happened
The conversation stays connected to the work.
- Streamed tool activity and results
- File diffs and guarded restore
- Plans and subagent activity with Ultra
- Saved local conversation history
A signed-in Codex account and the relevant FPGA tools are required. Hardware programming uses explicit approval for the target and artifact. Claude Code installation and sign-in are also available in settings.
GitHub integration
Your hardware project.
Ready to share.
Keep version control close to the design. Initialize Git at project creation, then open Publish to GitHub directly from the project explorer.
From local work to a repository.
Connect your GitHub account, review changed files, commit your work, and create or select a repository before pushing.
- Guided publishing workflow
- Changed-file status
- Existing or new repositories
- Git command mode
New repositories default to private. Your local projects work without a GitHub account.
One connected workflow
From the first line
to running hardware.
Start with a board or a board-free project. Editing, simulation, and hardware tools live together in the same workspace.
Start your project
Choose a target, open an existing folder, or ask Codex to create a design.
Make it work
Edit RTL, run testbenches, inspect waveforms, and interact with virtual hardware.
Take it to hardware
Map pins, synthesize, generate a bitstream, and program a supported board.
Standard HDL project filesVisible tool outputIndependent virtual and physical mappings
Explore the workspaces
Every tool.
The same project.
One dock brings the full workflow within reach. Explore each workspace below, or click a capture to see the details.
01 / Editor
Write RTL with room to focus.
A Monaco editor, shared project explorer, file tabs, and RTL hierarchy keep multi-file designs organized. Autosave keeps your source up to date as you move between tools.
02 / Testbench
Follow every signal.
Choose a testbench, run it with Icarus Verilog, and inspect the resulting VCD waveforms. An open waveform canvas sits alongside setup, files, and simulator logs.
03 / Synthesis
See the logic behind your RTL.
Run Yosys and review the design report. Open the Synthesis Explorer to navigate hierarchy, trace connections, inspect logic, and move back to the source.
04 / Pin Mapping
Connect the design to the board.
Assign RTL ports to physical resources in Simple or Advanced mode. Review assignments, board resources, validation, and generated constraints together.
05 / Bitstream
Build with the details in view.
Check build preflight and health, then run synthesis, placement, routing, and packing. Build Log, Health, and Bitstream Preview share one workspace. Review timing and build history in Health.
06 / Program
Meet the hardware.
Choose a generated bitstream and matching programmer, detect your board, and program it. The integrated Serial Monitor lets you inspect and send messages without leaving Program.
07 / Virtual FPGA
Try the hardware before you have it.
Compile real RTL with Verilator, map ports to virtual controls, and run, pause, step, or reset the design. Virtual FPGA is part of the same project dock.
Switch between editing, simulation, and hardware work from the shared dock.
Source files, board settings, generated assets, and AI work belong to the same project.
Inspect tool logs and results in the workspace that produced them.
Connected design tools
The Allora Link.
Three design tools that connect your RTL, peripherals, memory assets, and register maps. Use them alongside AI Design Studio and the core workspaces, from Home or the project dock.
01 / Connect your design
A visual workbench for your real RTL.
Arrange buttons, switches, LEDs, seven-segment displays, and a UART terminal. Connect each device to your RTL ports, then compile with Verilator to run, pause, and step through live behavior.
Devices, connections, and layout are saved with the project.
02 / Create memory assets
Turn images and data into FPGA memory.
Import images, binary files, or numeric tables. Preview monochrome, RGB565, indexed, integer, or fixed-point conversions, inspect the encoded words, and generate .hex files with an optional Verilog ROM.
Generated assets work with the editor, simulation, and physical builds.
03 / Define your interface
One register map for hardware and firmware.
Define registers, byte offsets, bit fields, resets, and access modes with a live bit layout and validation. Generate a SystemVerilog register bank, matching C header, JSON map, and wiring snippet.
Optional reviewed wrappers help connect the generated bank to your RTL.
Ice & Black Ice
A clear view.
In either light.
The same precise layout, frosted surfaces, and cool accents carry through every workspace. Choose Ice or Black Ice, then set the atmosphere with Refraction, Trace, or Molecules.
Room for the work
Open canvases keep code, waveforms, and logic in focus.
Useful detail
Compact inspectors keep setup and results close at hand.
One visual language
Shared controls make every workspace feel familiar.
Compare boards
Choose the right target.
Compare boards with an open build flow, then browse the wider pin-mapping catalog. Programming support depends on the board and programmer.
— open build
flow— pin mapping /
constraints
versus
Board catalogOpen builds and visual pin data in one place
No boards match that search.
Desktop app
Build your next idea here.
Native AI, connected workspaces, and the open FPGA toolchain. Allora FPGA for macOS is under active development. The installer will be available here when the first packaged release is ready.